Bare Metal Rust Afternoon

RTC driver

(back to exercise)

main.rs:

  1. #![no_main]
  2. #![no_std]
  4. mod exceptions;
  5. mod logger;
  6. mod pl011;
  7. mod pl031;
  9. use crate::pl031::Rtc;
  10. use arm_gic::gicv3::{IntId, Trigger};
  11. use arm_gic::{irq_enable, wfi};
  12. use chrono::{TimeZone, Utc};
  13. use core::hint::spin_loop;
  14. use crate::pl011::Uart;
  15. use arm_gic::gicv3::GicV3;
  16. use core::panic::PanicInfo;
  17. use log::{error, info, trace, LevelFilter};
  18. use smccc::psci::system_off;
  19. use smccc::Hvc;
  21. /// Base addresses of the GICv3.
  22. const GICD_BASE_ADDRESS: *mut u64 = 0x800_0000 as _;
  23. const GICR_BASE_ADDRESS: *mut u64 = 0x80A_0000 as _;
  25. /// Base address of the primary PL011 UART.
  26. const PL011_BASE_ADDRESS: *mut u32 = 0x900_0000 as _;
  28. /// Base address of the PL031 RTC.
  29. const PL031_BASE_ADDRESS: *mut u32 = 0x901_0000 as _;
  30. /// The IRQ used by the PL031 RTC.
  31. const PL031_IRQ: IntId = IntId::spi(2);
  33. // SAFETY: There is no other global function of this name.
  34. #[unsafe(no_mangle)]
  35. extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
  36.     // SAFETY: `PL011_BASE_ADDRESS` is the base address of a PL011 device, and
  37.     // nothing else accesses that address range.
  38.     let uart = unsafe { Uart::new(PL011_BASE_ADDRESS) };
  39.     logger::init(uart, LevelFilter::Trace).unwrap();
  41.     info!("main({:#x}, {:#x}, {:#x}, {:#x})", x0, x1, x2, x3);
  43.     // SAFETY: `GICD_BASE_ADDRESS` and `GICR_BASE_ADDRESS` are the base
  44.     // addresses of a GICv3 distributor and redistributor respectively, and
  45.     // nothing else accesses those address ranges.
  46.     let mut gic = unsafe { GicV3::new(GICD_BASE_ADDRESS, GICR_BASE_ADDRESS) };
  47.     gic.setup();
  49.     // SAFETY: `PL031_BASE_ADDRESS` is the base address of a PL031 device, and
  50.     // nothing else accesses that address range.
  51.     let mut rtc = unsafe { Rtc::new(PL031_BASE_ADDRESS) };
  52.     let timestamp = rtc.read();
  53.     let time = Utc.timestamp_opt(timestamp.into(), 0).unwrap();
  54.     info!("RTC: {time}");
  56.     GicV3::set_priority_mask(0xff);
  57.     gic.set_interrupt_priority(PL031_IRQ, 0x80);
  58.     gic.set_trigger(PL031_IRQ, Trigger::Level);
  59.     irq_enable();
  60.     gic.enable_interrupt(PL031_IRQ, true);
  62.     // Wait for 3 seconds, without interrupts.
  63.     let target = timestamp + 3;
  64.     rtc.set_match(target);
  65.     info!("Waiting for {}", Utc.timestamp_opt(target.into(), 0).unwrap());
  66.     trace!(
  67.         "matched={}, interrupt_pending={}",
  68.         rtc.matched(),
  69.         rtc.interrupt_pending()
  70.     );
  71.     while !rtc.matched() {
  72.         spin_loop();
  73.     }
  74.     trace!(
  75.         "matched={}, interrupt_pending={}",
  76.         rtc.matched(),
  77.         rtc.interrupt_pending()
  78.     );
  79.     info!("Finished waiting");
  81.     // Wait another 3 seconds for an interrupt.
  82.     let target = timestamp + 6;
  83.     info!("Waiting for {}", Utc.timestamp_opt(target.into(), 0).unwrap());
  84.     rtc.set_match(target);
  85.     rtc.clear_interrupt();
  86.     rtc.enable_interrupt(true);
  87.     trace!(
  88.         "matched={}, interrupt_pending={}",
  89.         rtc.matched(),
  90.         rtc.interrupt_pending()
  91.     );
  92.     while !rtc.interrupt_pending() {
  93.         wfi();
  94.     }
  95.     trace!(
  96.         "matched={}, interrupt_pending={}",
  97.         rtc.matched(),
  98.         rtc.interrupt_pending()
  99.     );
  100.     info!("Finished waiting");
  102.     system_off::<Hvc>().unwrap();
  103. }
  105. #[panic_handler]
  106. fn panic(info: &PanicInfo) -> ! {
  107.     error!("{info}");
  108.     system_off::<Hvc>().unwrap();
  109.     loop {}
  110. }

pl031.rs:

  1. #![allow(unused)]
  2. fn main() {
  3. #[repr(C, align(4))]
  4. struct Registers {
  5.     /// Data register
  6.     dr: u32,
  7.     /// Match register
  8.     mr: u32,
  9.     /// Load register
  10.     lr: u32,
  11.     /// Control register
  12.     cr: u8,
  13.     _reserved0: [u8; 3],
  14.     /// Interrupt Mask Set or Clear register
  15.     imsc: u8,
  16.     _reserved1: [u8; 3],
  17.     /// Raw Interrupt Status
  18.     ris: u8,
  19.     _reserved2: [u8; 3],
  20.     /// Masked Interrupt Status
  21.     mis: u8,
  22.     _reserved3: [u8; 3],
  23.     /// Interrupt Clear Register
  24.     icr: u8,
  25.     _reserved4: [u8; 3],
  26. }
  28. /// Driver for a PL031 real-time clock.
  29. #[derive(Debug)]
  30. pub struct Rtc {
  31.     registers: *mut Registers,
  32. }
  34. impl Rtc {
  35.     /// Constructs a new instance of the RTC driver for a PL031 device at the
  36.     /// given base address.
  37.     ///
  38.     /// # Safety
  39.     ///
  40.     /// The given base address must point to the MMIO control registers of a
  41.     /// PL031 device, which must be mapped into the address space of the process
  42.     /// as device memory and not have any other aliases.
  43.     pub unsafe fn new(base_address: *mut u32) -> Self {
  44.         Self { registers: base_address as *mut Registers }
  45.     }
  47.     /// Reads the current RTC value.
  48.     pub fn read(&self) -> u32 {
  49.         // SAFETY: We know that self.registers points to the control registers
  50.         // of a PL031 device which is appropriately mapped.
  51.         unsafe { (&raw const (*self.registers).dr).read_volatile() }
  52.     }
  54.     /// Writes a match value. When the RTC value matches this then an interrupt
  55.     /// will be generated (if it is enabled).
  56.     pub fn set_match(&mut self, value: u32) {
  57.         // SAFETY: We know that self.registers points to the control registers
  58.         // of a PL031 device which is appropriately mapped.
  59.         unsafe { (&raw mut (*self.registers).mr).write_volatile(value) }
  60.     }
  62.     /// Returns whether the match register matches the RTC value, whether or not
  63.     /// the interrupt is enabled.
  64.     pub fn matched(&self) -> bool {
  65.         // SAFETY: We know that self.registers points to the control registers
  66.         // of a PL031 device which is appropriately mapped.
  67.         let ris = unsafe { (&raw const (*self.registers).ris).read_volatile() };
  68.         (ris & 0x01) != 0
  69.     }
  71.     /// Returns whether there is currently an interrupt pending.
  72.     ///
  73.     /// This should be true if and only if `matched` returns true and the
  74.     /// interrupt is masked.
  75.     pub fn interrupt_pending(&self) -> bool {
  76.         // SAFETY: We know that self.registers points to the control registers
  77.         // of a PL031 device which is appropriately mapped.
  78.         let ris = unsafe { (&raw const (*self.registers).mis).read_volatile() };
  79.         (ris & 0x01) != 0
  80.     }
  82.     /// Sets or clears the interrupt mask.
  83.     ///
  84.     /// When the mask is true the interrupt is enabled; when it is false the
  85.     /// interrupt is disabled.
  86.     pub fn enable_interrupt(&mut self, mask: bool) {
  87.         let imsc = if mask { 0x01 } else { 0x00 };
  88.         // SAFETY: We know that self.registers points to the control registers
  89.         // of a PL031 device which is appropriately mapped.
  90.         unsafe { (&raw mut (*self.registers).imsc).write_volatile(imsc) }
  91.     }
  93.     /// Clears a pending interrupt, if any.
  94.     pub fn clear_interrupt(&mut self) {
  95.         // SAFETY: We know that self.registers points to the control registers
  96.         // of a PL031 device which is appropriately mapped.
  97.         unsafe { (&raw mut (*self.registers).icr).write_volatile(0x01) }
  98.     }
  99. }
  101. // SAFETY: `Rtc` just contains a pointer to device memory, which can be
  102. // accessed from any context.
  103. unsafe impl Send for Rtc {}
  104. }