RTC 驱动程序

QEMU aarch64 虚拟机在 0x9010000 地址处 配备了 PL031 实时时钟。对于本练习，应该为其编写驱动程序。

  1. 使用该时钟可将当前时间输出到串行控制台。您可以使用 chrono crate 设置日期/时间格式。
  2. 通过匹配寄存器和原始中断状态，使得系统在某段指定的时间内一直进行繁忙等待（例如 3 秒后）。（在循环操作中调用 core::hint::spin_loop。）
  3. _进行扩展（如有时间）：_启用并处理由 RTC 匹配产生的中断。可以使用 arm-gic crate 中提供的驱动程序来配置 Arm 通用中断控制器。
    • 请使用 RTC 中断，将其作为 IntId::spi(2) 连接到 GIC。
    • 启用中断后，可以通过 arm_gic::wfi() 让核心进入休眠状态，直到它收到中断信号。

下载 练习模板 并在 rtc 目录中查找以下文件。

src/main.rs:

  1. #![no_main]
  2. #![no_std]
  4. mod exceptions;
  5. mod logger;
  6. mod pl011;
  8. use crate::pl011::Uart;
  9. use arm_gic::gicv3::GicV3;
  10. use core::panic::PanicInfo;
  11. use log::{error, info, trace, LevelFilter};
  12. use smccc::psci::system_off;
  13. use smccc::Hvc;
  15. /// Base addresses of the GICv3.
  16. const GICD_BASE_ADDRESS: *mut u64 = 0x800_0000 as _;
  17. const GICR_BASE_ADDRESS: *mut u64 = 0x80A_0000 as _;
  19. /// Base address of the primary PL011 UART.
  20. const PL011_BASE_ADDRESS: *mut u32 = 0x900_0000 as _;
  22. #[no_mangle]
  23. extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
  24.     // SAFETY: `PL011_BASE_ADDRESS` is the base address of a PL011 device, and
  25.     // nothing else accesses that address range.
  26.     let uart = unsafe { Uart::new(PL011_BASE_ADDRESS) };
  27.     logger::init(uart, LevelFilter::Trace).unwrap();
  29.     info!("main({:#x}, {:#x}, {:#x}, {:#x})", x0, x1, x2, x3);
  31.     // SAFETY: `GICD_BASE_ADDRESS` and `GICR_BASE_ADDRESS` are the base
  32.     // addresses of a GICv3 distributor and redistributor respectively, and
  33.     // nothing else accesses those address ranges.
  34.     let mut gic = unsafe { GicV3::new(GICD_BASE_ADDRESS, GICR_BASE_ADDRESS) };
  35.     gic.setup();
  37.     // TODO: Create instance of RTC driver and print current time.
  39.     // TODO: Wait for 3 seconds.
  41.     system_off::<Hvc>().unwrap();
  42. }
  44. #[panic_handler]
  45. fn panic(info: &PanicInfo) -> ! {
  46.     error!("{info}");
  47.     system_off::<Hvc>().unwrap();
  48.     loop {}
  49. }

src/exceptions.rs（只需在本练习的第 3 部分更改此项）：

  1. #![allow(unused)]
  2. fn main() {
  3. // Copyright 2023 Google LLC
  4. //
  5. // Licensed under the Apache License, Version 2.0 (the "License");
  6. // you may not use this file except in compliance with the License.
  7. // You may obtain a copy of the License at
  8. //
  9. //      http://www.apache.org/licenses/LICENSE-2.0
  10. //
  11. // Unless required by applicable law or agreed to in writing, software
  12. // distributed under the License is distributed on an "AS IS" BASIS,
  13. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14. // See the License for the specific language governing permissions and
  15. // limitations under the License.
  17. use arm_gic::gicv3::GicV3;
  18. use log::{error, info, trace};
  19. use smccc::psci::system_off;
  20. use smccc::Hvc;
  22. #[no_mangle]
  23. extern "C" fn sync_exception_current(_elr: u64, _spsr: u64) {
  24.     error!("sync_exception_current");
  25.     system_off::<Hvc>().unwrap();
  26. }
  28. #[no_mangle]
  29. extern "C" fn irq_current(_elr: u64, _spsr: u64) {
  30.     trace!("irq_current");
  31.     let intid =
  32.         GicV3::get_and_acknowledge_interrupt().expect("No pending interrupt");
  33.     info!("IRQ {intid:?}");
  34. }
  36. #[no_mangle]
  37. extern "C" fn fiq_current(_elr: u64, _spsr: u64) {
  38.     error!("fiq_current");
  39.     system_off::<Hvc>().unwrap();
  40. }
  42. #[no_mangle]
  43. extern "C" fn serr_current(_elr: u64, _spsr: u64) {
  44.     error!("serr_current");
  45.     system_off::<Hvc>().unwrap();
  46. }
  48. #[no_mangle]
  49. extern "C" fn sync_lower(_elr: u64, _spsr: u64) {
  50.     error!("sync_lower");
  51.     system_off::<Hvc>().unwrap();
  52. }
  54. #[no_mangle]
  55. extern "C" fn irq_lower(_elr: u64, _spsr: u64) {
  56.     error!("irq_lower");
  57.     system_off::<Hvc>().unwrap();
  58. }
  60. #[no_mangle]
  61. extern "C" fn fiq_lower(_elr: u64, _spsr: u64) {
  62.     error!("fiq_lower");
  63.     system_off::<Hvc>().unwrap();
  64. }
  66. #[no_mangle]
  67. extern "C" fn serr_lower(_elr: u64, _spsr: u64) {
  68.     error!("serr_lower");
  69.     system_off::<Hvc>().unwrap();
  70. }
  71. }

src/logger.rs（无需对此进行更改）：

  1. #![allow(unused)]
  2. fn main() {
  3. // Copyright 2023 Google LLC
  4. //
  5. // Licensed under the Apache License, Version 2.0 (the "License");
  6. // you may not use this file except in compliance with the License.
  7. // You may obtain a copy of the License at
  8. //
  9. //      http://www.apache.org/licenses/LICENSE-2.0
  10. //
  11. // Unless required by applicable law or agreed to in writing, software
  12. // distributed under the License is distributed on an "AS IS" BASIS,
  13. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14. // See the License for the specific language governing permissions and
  15. // limitations under the License.
  17. // ANCHOR: main
  18. use crate::pl011::Uart;
  19. use core::fmt::Write;
  20. use log::{LevelFilter, Log, Metadata, Record, SetLoggerError};
  21. use spin::mutex::SpinMutex;
  23. static LOGGER: Logger = Logger { uart: SpinMutex::new(None) };
  25. struct Logger {
  26.     uart: SpinMutex<Option<Uart>>,
  27. }
  29. impl Log for Logger {
  30.     fn enabled(&self, _metadata: &Metadata) -> bool {
  31.         true
  32.     }
  34.     fn log(&self, record: &Record) {
  35.         writeln!(
  36.             self.uart.lock().as_mut().unwrap(),
  37.             "[{}] {}",
  38.             record.level(),
  39.             record.args()
  40.         )
  41.         .unwrap();
  42.     }
  44.     fn flush(&self) {}
  45. }
  47. /// Initialises UART logger.
  48. pub fn init(uart: Uart, max_level: LevelFilter) -> Result<(), SetLoggerError> {
  49.     LOGGER.uart.lock().replace(uart);
  51.     log::set_logger(&LOGGER)?;
  52.     log::set_max_level(max_level);
  53.     Ok(())
  54. }
  55. }

src/pl011.rs（无需对此进行更改）：

  1. #![allow(unused)]
  2. fn main() {
  3. // Copyright 2023 Google LLC
  4. //
  5. // Licensed under the Apache License, Version 2.0 (the "License");
  6. // you may not use this file except in compliance with the License.
  7. // You may obtain a copy of the License at
  8. //
  9. //      http://www.apache.org/licenses/LICENSE-2.0
  10. //
  11. // Unless required by applicable law or agreed to in writing, software
  12. // distributed under the License is distributed on an "AS IS" BASIS,
  13. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14. // See the License for the specific language governing permissions and
  15. // limitations under the License.
  17. #![allow(unused)]
  19. use core::fmt::{self, Write};
  20. use core::ptr::{addr_of, addr_of_mut};
  22. // ANCHOR: Flags
  23. use bitflags::bitflags;
  25. bitflags! {
  26.     /// Flags from the UART flag register.
  27.     #[repr(transparent)]
  28.     #[derive(Copy, Clone, Debug, Eq, PartialEq)]
  29.     struct Flags: u16 {
  30.         /// Clear to send.
  31.         const CTS = 1 << 0;
  32.         /// Data set ready.
  33.         const DSR = 1 << 1;
  34.         /// Data carrier detect.
  35.         const DCD = 1 << 2;
  36.         /// UART busy transmitting data.
  37.         const BUSY = 1 << 3;
  38.         /// Receive FIFO is empty.
  39.         const RXFE = 1 << 4;
  40.         /// Transmit FIFO is full.
  41.         const TXFF = 1 << 5;
  42.         /// Receive FIFO is full.
  43.         const RXFF = 1 << 6;
  44.         /// Transmit FIFO is empty.
  45.         const TXFE = 1 << 7;
  46.         /// Ring indicator.
  47.         const RI = 1 << 8;
  48.     }
  49. }
  50. // ANCHOR_END: Flags
  52. bitflags! {
  53.     /// Flags from the UART Receive Status Register / Error Clear Register.
  54.     #[repr(transparent)]
  55.     #[derive(Copy, Clone, Debug, Eq, PartialEq)]
  56.     struct ReceiveStatus: u16 {
  57.         /// Framing error.
  58.         const FE = 1 << 0;
  59.         /// Parity error.
  60.         const PE = 1 << 1;
  61.         /// Break error.
  62.         const BE = 1 << 2;
  63.         /// Overrun error.
  64.         const OE = 1 << 3;
  65.     }
  66. }
  68. // ANCHOR: Registers
  69. #[repr(C, align(4))]
  70. struct Registers {
  71.     dr: u16,
  72.     _reserved0: [u8; 2],
  73.     rsr: ReceiveStatus,
  74.     _reserved1: [u8; 19],
  75.     fr: Flags,
  76.     _reserved2: [u8; 6],
  77.     ilpr: u8,
  78.     _reserved3: [u8; 3],
  79.     ibrd: u16,
  80.     _reserved4: [u8; 2],
  81.     fbrd: u8,
  82.     _reserved5: [u8; 3],
  83.     lcr_h: u8,
  84.     _reserved6: [u8; 3],
  85.     cr: u16,
  86.     _reserved7: [u8; 3],
  87.     ifls: u8,
  88.     _reserved8: [u8; 3],
  89.     imsc: u16,
  90.     _reserved9: [u8; 2],
  91.     ris: u16,
  92.     _reserved10: [u8; 2],
  93.     mis: u16,
  94.     _reserved11: [u8; 2],
  95.     icr: u16,
  96.     _reserved12: [u8; 2],
  97.     dmacr: u8,
  98.     _reserved13: [u8; 3],
  99. }
  100. // ANCHOR_END: Registers
  102. // ANCHOR: Uart
  103. /// Driver for a PL011 UART.
  104. #[derive(Debug)]
  105. pub struct Uart {
  106.     registers: *mut Registers,
  107. }
  109. impl Uart {
  110.     /// Constructs a new instance of the UART driver for a PL011 device at the
  111.     /// given base address.
  112.     ///
  113.     /// # Safety
  114.     ///
  115.     /// The given base address must point to the MMIO control registers of a
  116.     /// PL011 device, which must be mapped into the address space of the process
  117.     /// as device memory and not have any other aliases.
  118.     pub unsafe fn new(base_address: *mut u32) -> Self {
  119.         Self { registers: base_address as *mut Registers }
  120.     }
  122.     /// Writes a single byte to the UART.
  123.     pub fn write_byte(&self, byte: u8) {
  124.         // Wait until there is room in the TX buffer.
  125.         while self.read_flag_register().contains(Flags::TXFF) {}
  127.         // SAFETY: We know that self.registers points to the control registers
  128.         // of a PL011 device which is appropriately mapped.
  129.         unsafe {
  130.             // Write to the TX buffer.
  131.             addr_of_mut!((*self.registers).dr).write_volatile(byte.into());
  132.         }
  134.         // Wait until the UART is no longer busy.
  135.         while self.read_flag_register().contains(Flags::BUSY) {}
  136.     }
  138.     /// Reads and returns a pending byte, or `None` if nothing has been
  139.     /// received.
  140.     pub fn read_byte(&self) -> Option<u8> {
  141.         if self.read_flag_register().contains(Flags::RXFE) {
  142.             None
  143.         } else {
  144.             // SAFETY: We know that self.registers points to the control
  145.             // registers of a PL011 device which is appropriately mapped.
  146.             let data = unsafe { addr_of!((*self.registers).dr).read_volatile() };
  147.             // TODO: Check for error conditions in bits 8-11.
  148.             Some(data as u8)
  149.         }
  150.     }
  152.     fn read_flag_register(&self) -> Flags {
  153.         // SAFETY: We know that self.registers points to the control registers
  154.         // of a PL011 device which is appropriately mapped.
  155.         unsafe { addr_of!((*self.registers).fr).read_volatile() }
  156.     }
  157. }
  158. // ANCHOR_END: Uart
  160. impl Write for Uart {
  161.     fn write_str(&mut self, s: &str) -> fmt::Result {
  162.         for c in s.as_bytes() {
  163.             self.write_byte(*c);
  164.         }
  165.         Ok(())
  166.     }
  167. }
  169. // Safe because it just contains a pointer to device memory, which can be
  170. // accessed from any context.
  171. unsafe impl Send for Uart {}
  172. }

Cargo.toml（无需对此进行更改）：

  1. [workspace]
  3. [package]
  4. name = "rtc"
  5. version = "0.1.0"
  6. edition = "2021"
  7. publish = false
  9. [dependencies]
  10. arm-gic = "0.1.0"
  11. bitflags = "2.5.0"
  12. chrono = { version = "0.4.37", default-features = false }
  13. log = "0.4.21"
  14. smccc = "0.1.1"
  15. spin = "0.9.8"
  17. [build-dependencies]
  18. cc = "1.0.94"

build.rs（无需对此进行更改）：

  1. // Copyright 2023 Google LLC
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. //      http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  15. use cc::Build;
  16. use std::env;
  18. fn main() {
  19.     #[cfg(target_os = "linux")]
  20.     env::set_var("CROSS_COMPILE", "aarch64-linux-gnu");
  21.     #[cfg(not(target_os = "linux"))]
  22.     env::set_var("CROSS_COMPILE", "aarch64-none-elf");
  24.     Build::new()
  25.         .file("entry.S")
  26.         .file("exceptions.S")
  27.         .file("idmap.S")
  28.         .compile("empty")
  29. }

entry.S（无需对此进行更改）：

  1. /*
  2.  * Copyright 2023 Google LLC
  3.  *
  4.  * Licensed under the Apache License, Version 2.0 (the "License");
  5.  * you may not use this file except in compliance with the License.
  6.  * You may obtain a copy of the License at
  7.  *
  8.  *     https://www.apache.org/licenses/LICENSE-2.0
  9.  *
  10.  * Unless required by applicable law or agreed to in writing, software
  11.  * distributed under the License is distributed on an "AS IS" BASIS,
  12.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13.  * See the License for the specific language governing permissions and
  14.  * limitations under the License.
  15.  */
  17. .macro adr_l, reg:req, sym:req
  18.     adrp \reg, \sym
  19.     add \reg, \reg, :lo12:\sym
  20. .endm
  22. .macro mov_i, reg:req, imm:req
  23.     movz \reg, :abs_g3:\imm
  24.     movk \reg, :abs_g2_nc:\imm
  25.     movk \reg, :abs_g1_nc:\imm
  26.     movk \reg, :abs_g0_nc:\imm
  27. .endm
  29. .set .L_MAIR_DEV_nGnRE,    0x04
  30. .set .L_MAIR_MEM_WBWA,    0xff
  31. .set .Lmairval, .L_MAIR_DEV_nGnRE | (.L_MAIR_MEM_WBWA << 8)
  33. /* 4 KiB granule size for TTBR0_EL1. */
  34. .set .L_TCR_TG0_4KB, 0x0 << 14
  35. /* 4 KiB granule size for TTBR1_EL1. */
  36. .set .L_TCR_TG1_4KB, 0x2 << 30
  37. /* Disable translation table walk for TTBR1_EL1, generating a translation fault instead. */
  38. .set .L_TCR_EPD1, 0x1 << 23
  39. /* Translation table walks for TTBR0_EL1 are inner sharable. */
  40. .set .L_TCR_SH_INNER, 0x3 << 12
  41. /*
  42.  * Translation table walks for TTBR0_EL1 are outer write-back read-allocate write-allocate
  43.  * cacheable.
  44.  */
  45. .set .L_TCR_RGN_OWB, 0x1 << 10
  46. /*
  47.  * Translation table walks for TTBR0_EL1 are inner write-back read-allocate write-allocate
  48.  * cacheable.
  49.  */
  50. .set .L_TCR_RGN_IWB, 0x1 << 8
  51. /* Size offset for TTBR0_EL1 is 2**39 bytes (512 GiB). */
  52. .set .L_TCR_T0SZ_512, 64 - 39
  53. .set .Ltcrval, .L_TCR_TG0_4KB | .L_TCR_TG1_4KB | .L_TCR_EPD1 | .L_TCR_RGN_OWB
  54. .set .Ltcrval, .Ltcrval | .L_TCR_RGN_IWB | .L_TCR_SH_INNER | .L_TCR_T0SZ_512
  56. /* Stage 1 instruction access cacheability is unaffected. */
  57. .set .L_SCTLR_ELx_I, 0x1 << 12
  58. /* SP alignment fault if SP is not aligned to a 16 byte boundary. */
  59. .set .L_SCTLR_ELx_SA, 0x1 << 3
  60. /* Stage 1 data access cacheability is unaffected. */
  61. .set .L_SCTLR_ELx_C, 0x1 << 2
  62. /* EL0 and EL1 stage 1 MMU enabled. */
  63. .set .L_SCTLR_ELx_M, 0x1 << 0
  64. /* Privileged Access Never is unchanged on taking an exception to EL1. */
  65. .set .L_SCTLR_EL1_SPAN, 0x1 << 23
  66. /* SETEND instruction disabled at EL0 in aarch32 mode. */
  67. .set .L_SCTLR_EL1_SED, 0x1 << 8
  68. /* Various IT instructions are disabled at EL0 in aarch32 mode. */
  69. .set .L_SCTLR_EL1_ITD, 0x1 << 7
  70. .set .L_SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0x1 << 28) | (0x1 << 29)
  71. .set .Lsctlrval, .L_SCTLR_ELx_M | .L_SCTLR_ELx_C | .L_SCTLR_ELx_SA | .L_SCTLR_EL1_ITD | .L_SCTLR_EL1_SED
  72. .set .Lsctlrval, .Lsctlrval | .L_SCTLR_ELx_I | .L_SCTLR_EL1_SPAN | .L_SCTLR_EL1_RES1
  74. /**
  75.  * This is a generic entry point for an image. It carries out the operations required to prepare the
  76.  * loaded image to be run. Specifically, it zeroes the bss section using registers x25 and above,
  77.  * prepares the stack, enables floating point, and sets up the exception vector. It preserves x0-x3
  78.  * for the Rust entry point, as these may contain boot parameters.
  79.  */
  80. .section .init.entry, "ax"
  81. .global entry
  82. entry:
  83.     /* Load and apply the memory management configuration, ready to enable MMU and caches. */
  84.     adrp x30, idmap
  85.     msr ttbr0_el1, x30
  87.     mov_i x30, .Lmairval
  88.     msr mair_el1, x30
  90.     mov_i x30, .Ltcrval
  91.     /* Copy the supported PA range into TCR_EL1.IPS. */
  92.     mrs x29, id_aa64mmfr0_el1
  93.     bfi x30, x29, #32, #4
  95.     msr tcr_el1, x30
  97.     mov_i x30, .Lsctlrval
  99.     /*
  100.      * Ensure everything before this point has completed, then invalidate any potentially stale
  101.      * local TLB entries before they start being used.
  102.      */
  103.     isb
  104.     tlbi vmalle1
  105.     ic iallu
  106.     dsb nsh
  107.     isb
  109.     /*
  110.      * Configure sctlr_el1 to enable MMU and cache and don't proceed until this has completed.
  111.      */
  112.     msr sctlr_el1, x30
  113.     isb
  115.     /* Disable trapping floating point access in EL1. */
  116.     mrs x30, cpacr_el1
  117.     orr x30, x30, #(0x3 << 20)
  118.     msr cpacr_el1, x30
  119.     isb
  121.     /* Zero out the bss section. */
  122.     adr_l x29, bss_begin
  123.     adr_l x30, bss_end
  124. 0:    cmp x29, x30
  125.     b.hs 1f
  126.     stp xzr, xzr, [x29], #16
  127.     b 0b
  129. 1:    /* Prepare the stack. */
  130.     adr_l x30, boot_stack_end
  131.     mov sp, x30
  133.     /* Set up exception vector. */
  134.     adr x30, vector_table_el1
  135.     msr vbar_el1, x30
  137.     /* Call into Rust code. */
  138.     bl main
  140.     /* Loop forever waiting for interrupts. */
  141. 2:    wfi
  142.     b 2b

exceptions.S（无需对此进行更改）：

  1. /*
  2.  * Copyright 2023 Google LLC
  3.  *
  4.  * Licensed under the Apache License, Version 2.0 (the "License");
  5.  * you may not use this file except in compliance with the License.
  6.  * You may obtain a copy of the License at
  7.  *
  8.  *     https://www.apache.org/licenses/LICENSE-2.0
  9.  *
  10.  * Unless required by applicable law or agreed to in writing, software
  11.  * distributed under the License is distributed on an "AS IS" BASIS,
  12.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13.  * See the License for the specific language governing permissions and
  14.  * limitations under the License.
  15.  */
  17. /**
  18.  * Saves the volatile registers onto the stack. This currently takes 14
  19.  * instructions, so it can be used in exception handlers with 18 instructions
  20.  * left.
  21.  *
  22.  * On return, x0 and x1 are initialised to elr_el2 and spsr_el2 respectively,
  23.  * which can be used as the first and second arguments of a subsequent call.
  24.  */
  25. .macro save_volatile_to_stack
  26.     /* Reserve stack space and save registers x0-x18, x29 & x30. */
  27.     stp x0, x1, [sp, #-(8 * 24)]!
  28.     stp x2, x3, [sp, #8 * 2]
  29.     stp x4, x5, [sp, #8 * 4]
  30.     stp x6, x7, [sp, #8 * 6]
  31.     stp x8, x9, [sp, #8 * 8]
  32.     stp x10, x11, [sp, #8 * 10]
  33.     stp x12, x13, [sp, #8 * 12]
  34.     stp x14, x15, [sp, #8 * 14]
  35.     stp x16, x17, [sp, #8 * 16]
  36.     str x18, [sp, #8 * 18]
  37.     stp x29, x30, [sp, #8 * 20]
  39.     /*
  40.      * Save elr_el1 & spsr_el1. This such that we can take nested exception
  41.      * and still be able to unwind.
  42.      */
  43.     mrs x0, elr_el1
  44.     mrs x1, spsr_el1
  45.     stp x0, x1, [sp, #8 * 22]
  46. .endm
  48. /**
  49.  * Restores the volatile registers from the stack. This currently takes 14
  50.  * instructions, so it can be used in exception handlers while still leaving 18
  51.  * instructions left; if paired with save_volatile_to_stack, there are 4
  52.  * instructions to spare.
  53.  */
  54. .macro restore_volatile_from_stack
  55.     /* Restore registers x2-x18, x29 & x30. */
  56.     ldp x2, x3, [sp, #8 * 2]
  57.     ldp x4, x5, [sp, #8 * 4]
  58.     ldp x6, x7, [sp, #8 * 6]
  59.     ldp x8, x9, [sp, #8 * 8]
  60.     ldp x10, x11, [sp, #8 * 10]
  61.     ldp x12, x13, [sp, #8 * 12]
  62.     ldp x14, x15, [sp, #8 * 14]
  63.     ldp x16, x17, [sp, #8 * 16]
  64.     ldr x18, [sp, #8 * 18]
  65.     ldp x29, x30, [sp, #8 * 20]
  67.     /* Restore registers elr_el1 & spsr_el1, using x0 & x1 as scratch. */
  68.     ldp x0, x1, [sp, #8 * 22]
  69.     msr elr_el1, x0
  70.     msr spsr_el1, x1
  72.     /* Restore x0 & x1, and release stack space. */
  73.     ldp x0, x1, [sp], #8 * 24
  74. .endm
  76. /**
  77.  * This is a generic handler for exceptions taken at the current EL while using
  78.  * SP0. It behaves similarly to the SPx case by first switching to SPx, doing
  79.  * the work, then switching back to SP0 before returning.
  80.  *
  81.  * Switching to SPx and calling the Rust handler takes 16 instructions. To
  82.  * restore and return we need an additional 16 instructions, so we can implement
  83.  * the whole handler within the allotted 32 instructions.
  84.  */
  85. .macro current_exception_sp0 handler:req
  86.     msr spsel, #1
  87.     save_volatile_to_stack
  88.     bl \handler
  89.     restore_volatile_from_stack
  90.     msr spsel, #0
  91.     eret
  92. .endm
  94. /**
  95.  * This is a generic handler for exceptions taken at the current EL while using
  96.  * SPx. It saves volatile registers, calls the Rust handler, restores volatile
  97.  * registers, then returns.
  98.  *
  99.  * This also works for exceptions taken from EL0, if we don't care about
  100.  * non-volatile registers.
  101.  *
  102.  * Saving state and jumping to the Rust handler takes 15 instructions, and
  103.  * restoring and returning also takes 15 instructions, so we can fit the whole
  104.  * handler in 30 instructions, under the limit of 32.
  105.  */
  106. .macro current_exception_spx handler:req
  107.     save_volatile_to_stack
  108.     bl \handler
  109.     restore_volatile_from_stack
  110.     eret
  111. .endm
  113. .section .text.vector_table_el1, "ax"
  114. .global vector_table_el1
  115. .balign 0x800
  116. vector_table_el1:
  117. sync_cur_sp0:
  118.     current_exception_sp0 sync_exception_current
  120. .balign 0x80
  121. irq_cur_sp0:
  122.     current_exception_sp0 irq_current
  124. .balign 0x80
  125. fiq_cur_sp0:
  126.     current_exception_sp0 fiq_current
  128. .balign 0x80
  129. serr_cur_sp0:
  130.     current_exception_sp0 serr_current
  132. .balign 0x80
  133. sync_cur_spx:
  134.     current_exception_spx sync_exception_current
  136. .balign 0x80
  137. irq_cur_spx:
  138.     current_exception_spx irq_current
  140. .balign 0x80
  141. fiq_cur_spx:
  142.     current_exception_spx fiq_current
  144. .balign 0x80
  145. serr_cur_spx:
  146.     current_exception_spx serr_current
  148. .balign 0x80
  149. sync_lower_64:
  150.     current_exception_spx sync_lower
  152. .balign 0x80
  153. irq_lower_64:
  154.     current_exception_spx irq_lower
  156. .balign 0x80
  157. fiq_lower_64:
  158.     current_exception_spx fiq_lower
  160. .balign 0x80
  161. serr_lower_64:
  162.     current_exception_spx serr_lower
  164. .balign 0x80
  165. sync_lower_32:
  166.     current_exception_spx sync_lower
  168. .balign 0x80
  169. irq_lower_32:
  170.     current_exception_spx irq_lower
  172. .balign 0x80
  173. fiq_lower_32:
  174.     current_exception_spx fiq_lower
  176. .balign 0x80
  177. serr_lower_32:
  178.     current_exception_spx serr_lower

idmap.S（无需对此进行更改）

  1. /*
  2.  * Copyright 2023 Google LLC
  3.  *
  4.  * Licensed under the Apache License, Version 2.0 (the "License");
  5.  * you may not use this file except in compliance with the License.
  6.  * You may obtain a copy of the License at
  7.  *
  8.  *     https://www.apache.org/licenses/LICENSE-2.0
  9.  *
  10.  * Unless required by applicable law or agreed to in writing, software
  11.  * distributed under the License is distributed on an "AS IS" BASIS,
  12.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13.  * See the License for the specific language governing permissions and
  14.  * limitations under the License.
  15.  */
  17. .set .L_TT_TYPE_BLOCK, 0x1
  18. .set .L_TT_TYPE_PAGE,  0x3
  19. .set .L_TT_TYPE_TABLE, 0x3
  21. /* Access flag. */
  22. .set .L_TT_AF, 0x1 << 10
  23. /* Not global. */
  24. .set .L_TT_NG, 0x1 << 11
  25. .set .L_TT_XN, 0x3 << 53
  27. .set .L_TT_MT_DEV, 0x0 << 2            // MAIR #0 (DEV_nGnRE)
  28. .set .L_TT_MT_MEM, (0x1 << 2) | (0x3 << 8)    // MAIR #1 (MEM_WBWA), inner shareable
  30. .set .L_BLOCK_DEV, .L_TT_TYPE_BLOCK | .L_TT_MT_DEV | .L_TT_AF | .L_TT_XN
  31. .set .L_BLOCK_MEM, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_NG
  33. .section ".rodata.idmap", "a", %progbits
  34. .global idmap
  35. .align 12
  36. idmap:
  37.     /* level 1 */
  38.     .quad        .L_BLOCK_DEV | 0x0            // 1 GiB of device mappings
  39.     .quad        .L_BLOCK_MEM | 0x40000000    // 1 GiB of DRAM
  40.     .fill        254, 8, 0x0            // 254 GiB of unmapped VA space
  41.     .quad        .L_BLOCK_DEV | 0x4000000000 // 1 GiB of device mappings
  42.     .fill        255, 8, 0x0            // 255 GiB of remaining VA space

image.ld（无需对此进行更改）：

  1. /*
  2.  * Copyright 2023 Google LLC
  3.  *
  4.  * Licensed under the Apache License, Version 2.0 (the "License");
  5.  * you may not use this file except in compliance with the License.
  6.  * You may obtain a copy of the License at
  7.  *
  8.  *     https://www.apache.org/licenses/LICENSE-2.0
  9.  *
  10.  * Unless required by applicable law or agreed to in writing, software
  11.  * distributed under the License is distributed on an "AS IS" BASIS,
  12.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13.  * See the License for the specific language governing permissions and
  14.  * limitations under the License.
  15.  */
  17. /*
  18.  * Code will start running at this symbol which is placed at the start of the
  19.  * image.
  20.  */
  21. ENTRY(entry)
  23. MEMORY
  24. {
  25.     image : ORIGIN = 0x40080000, LENGTH = 2M
  26. }
  28. SECTIONS
  29. {
  30.     /*
  31.      * Collect together the code.
  32.      */
  33.     .init : ALIGN(4096) {
  34.         text_begin = .;
  35.         *(.init.entry)
  36.         *(.init.*)
  37.     } >image
  38.     .text : {
  39.         *(.text.*)
  40.     } >image
  41.     text_end = .;
  43.     /*
  44.      * Collect together read-only data.
  45.      */
  46.     .rodata : ALIGN(4096) {
  47.         rodata_begin = .;
  48.         *(.rodata.*)
  49.     } >image
  50.     .got : {
  51.         *(.got)
  52.     } >image
  53.     rodata_end = .;
  55.     /*
  56.      * Collect together the read-write data including .bss at the end which
  57.      * will be zero'd by the entry code.
  58.      */
  59.     .data : ALIGN(4096) {
  60.         data_begin = .;
  61.         *(.data.*)
  62.         /*
  63.          * The entry point code assumes that .data is a multiple of 32
  64.          * bytes long.
  65.          */
  66.         . = ALIGN(32);
  67.         data_end = .;
  68.     } >image
  70.     /* Everything beyond this point will not be included in the binary. */
  71.     bin_end = .;
  73.     /* The entry point code assumes that .bss is 16-byte aligned. */
  74.     .bss : ALIGN(16)  {
  75.         bss_begin = .;
  76.         *(.bss.*)
  77.         *(COMMON)
  78.         . = ALIGN(16);
  79.         bss_end = .;
  80.     } >image
  82.     .stack (NOLOAD) : ALIGN(4096) {
  83.         boot_stack_begin = .;
  84.         . += 40 * 4096;
  85.         . = ALIGN(4096);
  86.         boot_stack_end = .;
  87.     } >image
  89.     . = ALIGN(4K);
  90.     PROVIDE(dma_region = .);
  92.     /*
  93.      * Remove unused sections from the image.
  94.      */
  95.     /DISCARD/ : {
  96.         /* The image loads itself so doesn't need these sections. */
  97.         *(.gnu.hash)
  98.         *(.hash)
  99.         *(.interp)
  100.         *(.eh_frame_hdr)
  101.         *(.eh_frame)
  102.         *(.note.gnu.build-id)
  103.     }
  104. }

Makefile（无需对此进行更改）：

  1. # Copyright 2023 Google LLC
  2. #
  3. # Licensed under the Apache License, Version 2.0 (the "License");
  4. # you may not use this file except in compliance with the License.
  5. # You may obtain a copy of the License at
  6. #
  7. #      http://www.apache.org/licenses/LICENSE-2.0
  8. #
  9. # Unless required by applicable law or agreed to in writing, software
  10. # distributed under the License is distributed on an "AS IS" BASIS,
  11. # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. # See the License for the specific language governing permissions and
  13. # limitations under the License.
  15. UNAME := $(shell uname -s)
  16. ifeq ($(UNAME),Linux)
  17.     TARGET = aarch64-linux-gnu
  18. else
  19.     TARGET = aarch64-none-elf
  20. endif
  21. OBJCOPY = $(TARGET)-objcopy
  23. .PHONY: build qemu_minimal qemu qemu_logger
  25. all: rtc.bin
  27. build:
  28.     cargo build
  30. rtc.bin: build
  31.     $(OBJCOPY) -O binary target/aarch64-unknown-none/debug/rtc $@
  33. qemu: rtc.bin
  34.     qemu-system-aarch64 -machine virt,gic-version=3 -cpu max -serial mon:stdio -display none -kernel $< -s
  36. clean:
  37.     cargo clean
  38.     rm -f *.bin

.cargo/config.toml（无需对此进行更改）：

  1. [build]
  2. target = "aarch64-unknown-none"
  3. rustflags = ["-C", "link-arg=-Timage.ld"]

使用 make qemu 在 QEMU 中运行代码。