Check cache false sharing

Generally speaking, cache false sharing is one processor modifies the data in one cache line, the cache protocol requires other processors who access the same data need to refresh the cache line. “perf c2c“ command is used to debug this issue.

Check following code:

  1. # cat false_share.c
  2. #include <omp.h>
  3. #define N 100000000
  4. #define THRAED_NUM 8
  5. int values[N];
  6. int main(void)
  7. {
  8. int sum[THRAED_NUM];
  9. #pragma omp parallel for
  10. for (int i = 0; i < THRAED_NUM; i++)
  11. {
  12. for (int j = 0; j < N; j++)
  13. {
  14. sum[i] += values[j] >> i;
  15. }
  16. }
  17. return 0;
  18. }

The size of sum array is 32 bytes on my X64 platform, and resides in one cache line. Because all 8 threads will write it simultaneously:

  1. sum[i] += values[j] >> i;

It will cause cache false sharing issue. Build and use “perf c2c record“ command to profile it:

  1. # gcc -fopenmp -g false_share.c -o false_share
  2. # perf c2c record ./false_share

Use “perf c2c report“ to analyze it, and “HITM“ event is the central issue:

  1. # perf c2c report --stdio
  2. ......
  3. =================================================
  4. Trace Event Information
  5. =================================================
  6. Total records : 65407
  7. ......
  8. LLC Misses to Local DRAM : 36.9%
  9. LLC Misses to Remote DRAM : 33.8%
  10. LLC Misses to Remote cache (HIT) : 0.0%
  11. LLC Misses to Remote cache (HITM) : 29.2%
  12. ......
  13. =================================================
  14. Shared Cache Line Distribution Pareto
  15. =================================================
  16. #
  17. # ----- HITM ----- -- Store Refs -- --------- Data address --------- ---------- cycles ---------- Total cpu Shared
  18. # Num Rmt Lcl L1 Hit L1 Miss Offset Node PA cnt Code address rmt hitm lcl hitm load records cnt Symbol Object Source:Line Node
  19. # ..... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ .................. ........... ................ ....
  20. #
  21. -------------------------------------------------------------
  22. 0 41 446 159354 22984 0x7fff35cd5c40
  23. -------------------------------------------------------------
  24. 58.54% 59.19% 0.00% 0.00% 0x18 0 1 0x55bfa7082232 1734 1122 1150 72662 14 [.] main._omp_fn.0 false_share false_share.c:17 0 1
  25. 41.46% 38.57% 0.00% 0.00% 0x18 0 1 0x55bfa7082264 1341 1186 1151 71575 14 [.] main._omp_fn.0 false_share false_share.c:17 0 1
  26. 0.00% 0.00% 3.90% 1.41% 0x20 0 1 0x55bfa708226d 0 0 0 6541 1 [.] main._omp_fn.0 false_share false_share.c:17 1
  27. 0.00% 0.67% 0.00% 0.00% 0x24 0 1 0x55bfa708223b 0 4398 42 1484 1 [.] main._omp_fn.0 false_share false_share.c:17 0
  28. 0.00% 0.00% 13.84% 14.21% 0x24 0 1 0x55bfa708226d 0 0 0 25327 2 [.] main._omp_fn.0 false_share false_share.c:17 0
  29. 0.00% 0.67% 0.00% 0.00% 0x28 0 1 0x55bfa708223b 0 1262 43 1498 1 [.] main._omp_fn.0 false_share false_share.c:17 0
  30. 0.00% 0.00% 13.99% 14.04% 0x28 0 1 0x55bfa708226d 0 0 0 25520 2 [.] main._omp_fn.0 false_share false_share.c:17 0
  31. 0.00% 0.22% 0.00% 0.00% 0x2c 0 1 0x55bfa708223b 0 694 44 1661 1 [.] main._omp_fn.0 false_share false_share.c:17 0
  32. 0.00% 0.00% 13.60% 16.43% 0x2c 0 1 0x55bfa708226d 0 0 0 25449 1 [.] main._omp_fn.0 false_share false_share.c:17 0
  33. 0.00% 0.00% 14.00% 13.86% 0x30 0 1 0x55bfa708226d 0 0 0 25501 2 [.] main._omp_fn.0 false_share false_share.c:17 0
  34. 0.00% 0.22% 0.00% 0.00% 0x34 0 1 0x55bfa708223b 0 1742 42 1548 1 [.] main._omp_fn.0 false_share false_share.c:17 0
  35. 0.00% 0.00% 13.14% 12.81% 0x34 0 1 0x55bfa708226d 0 0 0 23880 2 [.] main._omp_fn.0 false_share false_share.c:17 0
  36. 0.00% 0.22% 0.00% 0.00% 0x38 0 1 0x55bfa708223b 0 286 42 1467 1 [.] main._omp_fn.0 false_share false_share.c:17 0
  37. 0.00% 0.00% 14.08% 13.62% 0x38 0 1 0x55bfa708226d 0 0 0 25569 2 [.] main._omp_fn.0 false_share false_share.c:17 0
  38. 0.00% 0.22% 0.00% 0.00% 0x3c 0 1 0x55bfa708223b 0 278 44 1420 2 [.] main._omp_fn.0 false_share false_share.c:17 0
  39. 0.00% 0.00% 13.44% 13.62% 0x3c 0 1 0x55bfa708226d 0 0 0 24551 2 [.] main._omp_fn.0 false_share false_share.c:17 0

The nifty feature is the report shows which line of source code causes cache false sharing.

Modify the code to avoid false sharing:

  1. #include <omp.h>
  2. #define N 100000000
  3. #define THRAED_NUM 8
  4. int values[N];
  5. int main(void)
  6. {
  7. int sum[THRAED_NUM];
  8. #pragma omp parallel for
  9. for (int i = 0; i < THRAED_NUM; i++)
  10. {
  11. int local_sum;
  12. for (int j = 0; j < N; j++)
  13. {
  14. local_sum += values[j] >> i;
  15. }
  16. sum[i] = local_sum;
  17. }
  18. return 0;
  19. }

This time the “perf c2c report“ outputs a very beautiful summary:

  1. =================================================
  2. Trace Event Information
  3. =================================================
  4. ......
  5. LLC Misses to Local DRAM : 88.7%
  6. LLC Misses to Remote DRAM : 9.9%
  7. LLC Misses to Remote cache (HIT) : 0.0%
  8. LLC Misses to Remote cache (HITM) : 1.4%
  9. ......